Synthesis tools are used to define an IC design and/or to map the design to a technology that is used to manufacture the IC. Such tools typically receive a design in one particular format and then perform a series of transformations on this format to define the design in another particular format. For instance, some synthesis tools receive the IC design in a register transfer language (RTL) format, and through a series of transformations, produce a circuit representation of the design that has been mapped to the technology used to manufacture the IC.
In performing the transformations, synthesis tools often must select between various available implementations for a given segment or function of the design. Typically, the synthesis tools make these decisions without sufficient data regarding constraints (e.g., timing data, area data, etc.) on the design. For example, a synthesizer might need to select a particular implementation of an adder. While different implementations of the adder may be functionally equivalent, the adders are not structurally equivalent. As such, each implementation is associated with different timing characteristics, area characteristics, etc. The synthesizer might need to select between the different adder implementations early in the synthesis flow. At the early stages, the synthesizer may not have sufficient constraint information (e.g., timing information about the expected signal delay or congestion information) to determine which of the viable options best satisfies the constraints. In such situations, synthesizers typically make greedy decisions that are not based on realistic data regarding design constraints.
Some synthesis tools today work in conjunction with placement tools during a multi-stage electronic design automation (EDA) process to improve the overall placement of the design. For instance, when a placer determines that a particular set of circuit modules in the design violates a particular design constraint, the placer will direct a synthesizer to provide an alternative implementation for the particular set of circuit modules to satisfy the particular design constraint. In response to such a request, the synthesizer might provide a better solution for the particular set of circuit modules that satisfies the particular design constraint. However, the new solution of the synthesizer might adversely affect the placement of other circuit modules causing the other circuit modules to violate one or more design constraints. This results in a cascading effect where a change in any one location of the design affects other circuits elsewhere within the design. As such, the prior art processes are prone to iteratively repeating until a preferred solution is determined that not only satisfies constraints for a particular implementation for a set of circuits, but that also satisfies constraints for other circuit modules affected by the placement of the particular selected implementation for the set of circuit modules. Such iterative repeating requires an exponential number of computations to converge to a solution that satisfies all constraints.
The cascading effect further causes a continual back and forth between the synthesis tool and other constraint analysis tools (e.g., a placement or routing engine). Every solution produced by the synthesis tool that does not satisfy the subsequent constraint analysis is returned to the synthesis tool with the constraint information in order for the synthesis tool to identify an alternative solution. The synthesis tool then determines an alternative solution and passes the alternative solution back to the constraint analysis tool for further constraint analysis. Such a back and forth between the synthesis tool and the constraint analysis tools is highly resource intensive (e.g., memory and/or processor) and time consuming.
Alternatively, some synthesis tools refrain from selecting between one of the viable options until the necessary information is available. To do so, each possible option is divided into a separate netlist before being passed to the constraint analysis tools. The constraint analysis tools then perform the constraint analysis on each option to determine which of the options is the preferred solution. Such an approach, while avoiding the continual back and forth between the synthesis tools and the constraint analysis tools, becomes infeasible for large scale designs where the netlist for every viable option consumes memory and the analysis of each netlist consumes processing resources of a computer system.
Therefore, there is a need in the art to leverage constraint data to select a preferred solution from amongst a set of viable solutions. However, since the constraint data may not be known until a later stage within the design process, there is a need to retain an exponential number of viable options across several stages of the design process using only a linear representation for the exponential number of options. Furthermore, selection of the preferred option should be allowed at any stage of the process without having to revert to previous stages within the EDA design process.